1. Field of the Invention
The present invention relates to a clock generating circuit, and more particularly to a fractional phase lock loop having an integral phase lock loop inside, wherein the feedback loop of the integral phase lock loop has a fixed frequency-dividing parameter.
2. Description of the Related Art
Because the fractional phase lock loop exhibits flexibility in selecting reference frequency, bandwidth and channel step size, it has been widely used in the transceiver of the Radio Frequency (RF) components.
FIG. 1 shows a prior art fractional phase lock loop 10, where a reference frequency Fref, a fixed frequency, e.g., 24 MHz, is generated by a crystal 14. A voltage-controlled oscillator (VCO) 12 has an output frequency Fvco=Ndiv×Fref, where Ndiv is the counting value of an N counter 13. The counting value Ndiv is an integer and controlled under the delta sigma modulator (DSM) 15. During a certain period, the counting value Ndiv varies within a certain numerical range. Over time, the average of the counting value Ndiv will approximate to a non-integral value N.fdiv, where N is an integral part, and fdiv is a decimal part. For example, as shown in FIG. 1, the integral and decimal parts can be controlled by inputting digital signals with 6 bits plus 19 bits into the delta sigma modulator 15. Therefore the output frequency Fvco=Fref×N.fdiv will be affected by the counting value of the N counter 13. The prior art fractional phase lock loop 10 achieves its purpose mainly by modulating Ndiv. However, the timing at which the control value outputted by the delta sigma modulator 15 is loaded by the N counter 13 has to be very accurate, and with greater values of the counting value Ndiv is, the frequency of the input signal of the N counter 13 must be accordingly higher. Because the prior art exhibits such characteristic, the requirement for timing must be stricter, and thus causes difficulties in design and increases cost.
A dual-modulus divider as shown in FIG. 2 was proposed to resolve a high frequency problem faced by the N counter 13. The dual-modulus divider 20 uses a prescalar 21 with divider equal to 16 or 17 and a pulse swallow counter 22 to decrease the output frequency Fvco so as to obtain a looser loading mechanism for the N counter 13 to load the control value. However, unless the timing is readjusted, other problems such as jitters and phase noises will likely occur.